An integrated circuit implementing a complex SoC needs to be accessed for functional and non functional purposes due to a number of reasons namely external configuration, observation and control, maintenance and updates.
SoCs have to adapt to a number of external circumstances, environments and standards. To accomplish this flexibility, configuration registers are used to store configuration values which influence the behavior of IP cores. Moreover, it is often necessary to issue commands while the IP core is working, and to monitor its state; this is normally accomplished by means of control and status registers. Comprehensive information about the state of the system or extensive programming can be obtained by dumping or uploading the entire contents of internal memories.
Previous schemes have been proposed to access integrated circuits for control, observation and configuration purposes. These functions tend to be separate from other communication functions and to use specific pins. Traditional schemes are normally low-speed serial protocols, which avoid using too many chip pins. Well known examples of such schemes include the I2C bus from Philips [1] or the SPI bus from Motorola [2]. The JTAG standard, initially developed for test purposes, has also become a major chip configuration and verification method and has been standardized by IEEE Std 1149.1 [3].
Field Programmable Gate Arrays (FPGAs) use Joint Test Action Group (JTAG) for chip configuration. Since FPGAs are fully configurable chips, they require massive amounts of configuration data, which, when input using JTAG, take a long time to upload on the chip.
FPGA vendors have developed proprietary configuration methods other than JTAG for providing shorter configuration times. These schemes normally use a parallel interface and load the configuration data from an external PROM, which is less flexible then getting the configuration data from a computer as with JTAG.
A known difficulty with JTAG is when only part of the chip needs to be reconfigured. To solve this problem, FPGA vendors have offered partial reconfiguration schemes which divide the chip in regions and allow reconfiguration of each region. However, these regions have to be large or otherwise the configuration setup overhead is too big. On the other hand I2C and SPI can be used to read or write small configuration registers but lack the ability to handle large amounts of configuration data.
An even more advanced feature is run-time reconfiguration. In some applications it has been proven advantageous to reconfigure the whole or parts of the chip while the application is running. This improves hardware utilization, saves area and improves performance. Infrastructure for runtime reconfiguration needs to be fast enough so that the reconfiguration time does not impact the computation time significantly. Additionally, reconfiguration needs to occur synchronously to the system clock, which is normally difficult to guarantee as configuration schemes tend to use their own clock domain. Traditional configuration schemes are bad for this purpose since they are slow and use a dedicated serial clock, distinct from the system clock.
With traditional configuration schemes, a configurable device can be programmed via the network if it is attached to a computer which is connected to the network. However, since the traditional configuration schemes are low-speed, any activity which requires data to be sent or received at speed from the device cannot be performed. Such activities include verification, debug, test, rapid partial and runtime configuration.
The schemes mentioned above are meant to access chips. With the current levels of system integration, printed circuit boards have been replaced with SoCs, where components are now embedded cores integrated in single silicon die. Thus, instead of accessing chips the need now arises to access cores inside the SoC. The IEEE 1500 standard is an extension of IEEE 1149 and proposes a means for accessing embedded cores for test. However, its main limitation is the fact that it implements a serial protocol and requires a long scan-chain to be implemented in the SoC. The result is slow stimuli application and response retrieval. Also a scan-chain does not follow the inherently hierarchical structure of digital circuits, and additional mechanisms such as defined in patent application US2003/120986 are needed to work hierarchically with this scheme.
This invention addresses all the problems mentioned above by embedding control, observation and configuration within the chip communication infrastructure itself, using a standard network interface embedded in the system. This way, the communication to the outside of the chip is high-speed serial, whereas the core to core internal communication is lower speed, parallel and memory mapped. Chip control, observation and configuration can be achieved without need for special fixtures and debug equipment such as JTAG pods and cables. Transactions can be achieved at the speed of communication networks, which provides much more bandwidth than traditional access schemes. Partial reconfiguration is facilitated by means of the proposed scheme, since the scheme is hierarchical and the configuration registers are addressable. Runtime reconfiguration is also made easier since the whole system is synchronous. With this invention the IP cores inside an SoC become networked devices in their own right. Thus, they can be directly accessed for verification, testing, field maintenance and firmware updates.